Renesas Electronics /R7FA6T2BD /SCI_B0 /CCR1

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Interpret as CCR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)CTSE 0 (0)CTSPEN 0 (0)SPB2DT 0 (0)SPB2IO 0 (0)PE 0 (0)PM 0 (0)TINV 0 (0)RINV 0 (0)SPLP 0 (0)SHARPS 0 (others)NFCS0 (0)NFEN

NFCS=others, SPB2IO=0, PE=0, CTSPEN=0, PM=0, TINV=0, NFEN=0, SPLP=0, SPB2DT=0, CTSE=0, SHARPS=0, RINV=0

Description

Common Control Register 1

Fields

CTSE

CTS Enable

0 (0): CTS function is disabled (RTS output function is enabled).

1 (1): CTS function is enabled.

CTSPEN

CTS external pin Enable

0 (0): Alternate setting to use CTS and RTS functions as either one pin

1 (1): Dedicated setting for separately using CTS and RTS functions with 2 pins

SPB2DT

Serial port break data select

0 (0): When TINV is 0, Low level is output in TXDn pin. When TINV is 1, High level is output in TXDn pin.

1 (1): When TINV is 0, High level is output in TXDn pin. When TINV is 1, Low level is output in TXDn pin.

SPB2IO

Serial port break I/O

0 (0): The value of SPB2DT bit is not output in TXDn pin.

1 (1): The value of SPB2DT bit is output in TXDn pin.

PE

Parity Enable

0 (0): When transmitting: Do not add parity bit When receiving: Do not check parity bit

1 (1): When transmitting: Add parity bit When receiving: Check parity bit

PM

Parity Mode

0 (0): Selects even parity

1 (1): Selects odd parity

TINV

TXD invert

0 (0): Transmit data is not inverted and output to TXDn.

1 (1): Transmit data is inverted and output to TXDn.

RINV

RXD invert

0 (0): Received data from RXDn is not inverted and input.

1 (1): Received data from RXDn is inverted and input.

SPLP

Loopback Control

0 (0): Normal mode

1 (1): Loopback mode

SHARPS

Half-duplex communication select

0 (0): TXDn pin, RXDn pin independent

1 (1): TXDn / RXDn pin combination use (Half-duplex communication using TXDn pin)

NFCS

Noise Filter Clock Select

0 (000): The base clock signal divided by 1.

0 (others): Setting prohibited.

1 (001): The on-chip baud rate generator source clock divided by 1.

2 (010): The on-chip baud rate generator source clock divided by 2.

3 (011): The on-chip baud rate generator source clock divided by 4.

4 (100): The on-chip baud rate generator source clock divided by 8.

NFEN

Digital Noise Filter Function Enable

0 (0): In Asynchronous, Manchester, Simple LIN mode: Disable noise cancellation function for RXDn input signal In Simple IIC mode: Disable noise cancellation function for SCLn and SDAn input signals

1 (1): In Asynchronous, Manchester, Simple LIN mode: Enable noise cancellation function for RXDn input signal In Simple IIC mode: Enable noise cancellation function for SCLn and SDAn input signals

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